The Nifty Chips Laboratory @ HYU

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The Nifty Chips Laboratory at Hanyang University is working on cool circuits and their automatic generators.

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Nifty Chips

A 18-Gb/s Variation-Tolerant Transmitter

chip17
Process: 28nm CMOS
Tapeout Year: 2022

A 28-Gb/s Single-Ended PAM-4 Receiver

chip16
Process: 40nm CMOS
Tapeout Year: 2022

A 35-Gb/s PAM-4 Transmitter

chip15
Process: 28nm CMOS
Tapeout Year: 2022

A 100-Gb/s PAM-8 Transmitter

chip14
Process: 40nm CMOS
Tapeout Year: 2021

An Asynchronous Sampling Duty-Cycle Corrector

chip12
Process: 40nm CMOS
Tapeout Year: 2021

A Transition-Limited Pulse-Amplitude Modulation Transmitter Prototype

chip11
Process: FPGA+DAC board
Year of Implementation: 2022

A 8-channel SDCSL Transceiver Array for Short-Reach Interconnects

chip10
Process: 28nm CMOS
Tapeout Year: 2021

A 12Gb/s Baud-rate CDR with Integration-Hold-Reset Frontend

chip9
Process: 28nm CMOS
Tapeout Year: 2021

Protective PRAM Sensors Prototype

chip8
Process: 180nm CMOS
Tapeout Year: 2021

A Loop-Unrolled 1.5GS/s SAR ADC

chip7
Process: 28nm CMOS
Tapeout Year: 2021

A PAM4 Driver Prototype

chip6
Process: 40nm CMOS
Tapeout Year: 2020

A 4-wire Balanced-Single-Ended Signaling Transceiver Array

chip13
Process: 28nm CMOS
Tapeout Year: 2019

A Generated 7GS/s 8b Time-Interleaved SAR ADC Integrated to a Signal Analysis SoC

chip5
Process: 16nm CMOS FinFET
Tapeout Year: 2016

A Generated SAR ADC Prototype

chip4
Process: 28nm CMOS
Tapeout Year: 2015

A Complete 60Gb/s Transceiver

chip3
Process: 65nm CMOS
Tapeout Year: 2015

A 60Gb/s Receiver Frontend

chip2
Process: 65nm CMOS
Tapeout Year: 2014

A 5Gb/s Digitally-Controlled Decision Feedback Equalizer

chip1
Process: 130nm CMOS
Tapeout Year: 2008

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