Nifty Papers

Peer-reviewed Journal Articles

2024

S. Lee, H. Seo, W. Shin, D. Yang, G. Sung, S. Lee, D. Choi, Y. Kwak, S. Won, I. Song, and J. Han, “A Variation-Robust 20-Gb/s Wireline Transceiver With Real-Time Calibration in 28-nm CMOS,” IEEE Trans. Circuits Syst. I: Regular Papers, Dec. 2024.

E. Song, J. Yang, Y. Oh, S. Hong, D. Lee, S. Lee, and J. Han, “100–112-Gb/s 1.6-Vppd PAM-8 Transmitters With High-Swing 3 + 1 Hybrid FFE Taps in 40-nm Technology,” IEEE J. Solid-State Circuits, Nov. 2024.

S. Lee, H. Seo, S. Son, S. Yeom, and J. Han, “A 102-Gb/s/lane 1.4-Vppd Linear Range PAM-8 Receiver Frontend With Multi-Path Continuous-Time Linear Equalization in 28-nm CMOS,” IEEE Trans. Circuits Syst. II: Express Briefs, vol. 71, no. 11, pp. 4623-4627, Nov. 2024.

[삼성전자 우수논문상] H. Kim, Y. Jo, S. Lee, E. Lee, Y. Choi, J. Park, M. Kwak, J. Choi, Y. Choi, and J. Han, “A 32-Gb/s Single-Ended PAM-4 Transceiver With Asymmetric Termination and Equalization Techniques for Next-Generation Memory Interfaces,” IEEE Trans. Circuits Syst. I: Regular Papers, vol. 71, no. 11, pp. 4912-4923, Nov. 2024.

T. Kim, G. Kim, M.-K. Cho, J. D. Cressler, J. Han, and I. Song, “Investigation of Device- and Circuit-Level Reliability of Inverse-Mode Silicon-Germanium Heterojunction Bipolar Transistors,” MDPI Sensors, Nov. 2024.

G. Park, S. Yeom, I.-W. Jang, D. Lee, Jaeduk Han, and Min-Seong Choo, “3.2-GHz Digital Phase-Locked Loop With Autocorrelation-Based Direct Jitter Correction,” IEEE Trans. Circuits Syst. II: Express Briefs, vol. 71, no. 9, pp. 4091-4095, Sep. 2024.

E. Lee, S. Lee, C. Pyo, H. Kim, and J. Han, “A 2-GS/s 6-bit Single-Channel Speculative Loop-Unrolled SAR ADC with Low-Overhead Comparator Offset Calibration in 28-nm CMOS,” J. Semicond. Technol. Sci., Aug. 2024.

G. You, Y. Byun, S. Lim, and J. Han, “Interactive and Automatic Generation of Primitive Custom Circuit Layout Using LLMs,” arXiv, Aug. 2024.

S. Hong, Y. Tae, D. Lee, G. Park, J. Lim, K. Cho, C. Jeong, M.-J. Park, and J. Han, “Analog Circuit Design Automation via Sequential RL Agents and gm/ID Methodology,” IEEE Access, vol. 12, pp. 104473-104489, Aug. 2024.

S. Lee, J. Lim, and J. Han, “A PSRR-Enhanced Fast-Response Inverter-Based LDO for Mobile Devices,” IEEE Trans. Circuits Syst. II: Express Briefs, Vol. 71, No. 6, pp. 3226-3230, Jun. 2024.

Y. Oh, H. Im, J. Yang, E. Song, D. Lee, S. Lee, T. Shin, and J. Han, “A 100-Gb/s PAM-8 Transmitter With 3-Tap FFE and High-Swing Hybrid Driver in 40-nm CMOS Technology,” IEEE Trans. Circuits Syst. II: Express Briefs, Vol. 71, No. 6, pp. 2936-2940, Jun. 2024.

W. Shin, H. Seo, S. Lee, D.-H. Choi, Y.-H. Kwak, S.-J. Won, and J. Han, “A Variation-Tolerant Voltage-Mode Transmitter With 3+1 Tap FFE in 28-nm CMOS,” IEEE Trans. Circuits Syst. II: Express Briefs, Vol. 71, No. 4, pp. 1819 - 1823, Apr. 2024.

T. Sim, S. Yeom, H. Im, Y. Oh, H. Seo, H. Ko, H. Chi, H. Jung, and J. Han, “A 28-Gb/s Single-Ended PAM-4 Receiver With T-Coil-Integrated Continuous-Time Linear Equalizer in 40-nm CMOS Technology,” IEEE Trans. Circuits Syst. II: Express Briefs, Vol. 71, No. 3, pp. 1012-1016, Mar. 2024.

E. Song, J. Han, H. Seo, H. Kim, H. Im, and J. Han, “A 35-Gb/s PAM-4 Transmitter with 7B4Q Full-Transition Avoidance and Area-Efficient Gm-Boosting Technique,” IEEE Trans. Circuits Syst. II: Express Briefs, Vol. 71, No. 1, pp. 46-50, Jan. 2024.

2023

T. Shin, D. Lee, D. Kim, G. Sung, W. Shin, Y. Jo, H. Park, and J. Han, “LAYGO2: A Custom Layout Generation Engine Based on Dynamic Templates and Grids for Advanced CMOS Technologies,” IEEE Trans. Comput.-Aided Des. Integr., Vol. 42, No. 10, pp. 4402-4412, Dec. 2023.

K. Kim, S. Moon, J. Han, E. Alon, and A. M. Niknejad, “Precursor ISI Cancellation Sliding-Block DFE for High-Speed Wireline Receivers,” IEEE Trans. Circuits Syst. I: Regular Papers, Vol. 70, No. 10, pp. 4169-4182, Aug. 2023.

H. Kim, H. Seo, H. Kim, C. Yoo, and J. Han, “A 16-Gb/s/wire 4-Wire Short-Haul Transceiver with Balanced Single-Ended Signaling (BASES) in 28-nm CMOS,” IEEE Trans. Circuits Syst. II: Express Briefs, Aug. 2023.

G. Park, D. Lee, J. Han, and W. Bae, “A High-Frequency and Low-Jitter DLL with Quadrature Error and Duty Cycle Corrections Based on Asynchronous Sampling,” IEEE Solid-State Circuits Letters, Feb. 2023.

H. Kim, H. Seo, Y. Jo, C. Yoo, and J. Han, “An 8b9b 77.44-Gb/s Noise-Immune Spatial-Delta Coded Transceiver for Short-Reach Memory Interfaces in 28-nm CMOS,” IEEE Trans. Circuits Syst. II: Express Briefs, Mar. 2023.

H. Seo, J. Han, K. Kim, B. Lim, E. Shin, Y. Choi, H. Ko, J. Choi, S. Lee, C. Yoo, and J. Han, “A 12-Gb/s Baud-rate Clock and Data Recovery with 75% Phase-detection Probability by Precoding and Integration-Hold-Reset Frontend,” IEEE Trans. Circuits Syst. II: Express Briefs, Feb. 2023.

D. Lee, G. Park, J. Han, and M.-S. Choo, “An Automated Design Methodology for Ring Voltage-Controlled Oscillators in Nanometer CMOS Technologies,” IEEE Access, Vol. 11, pp. 7530-7539, Jan. 2023.

2022

E. Song, S. Park, and J. Han, “Transition-Limited Pulse-Amplitude Modulation Technique for High-Speed Wireline Communication Systems,” ETRI J., Nov. 2022.

E. Lee, and J. Han, “Time-domain Continuous-time Delta-sigma Modulator using VCO-based Integrator and GRO-based Quantizer,” J. Semicond. Technol. Sci., Aug. 2022.

E. Lee, C. Pyo, S. Lee, and J. Han, “A 1.5-GS/s 6-bit Single-Channel Loop-Unrolled SAR ADC With Speculative CDAC Switching Control Technique in 28-nm CMOS,” IEEE Trans. Circuits Syst. I: Regular Papers, Jun. 2022.

T. No, S. Choi, G. Sung, S.-B. Kim, J. Han, and Y.-H. Song, “A Discharge-Path-Based Sensing Circuit with OTS Snapback Current Protection for Phase Change Memories,” IEEE Access, vol. 10, pp. 53513-53521, May 2022.

2021

G. Park, J. Han, and W. Bae, “Design and Analysis of Asynchronous Sampling Duty Cycle Corrector,” MDPI Electronics, Oct. 2021.

Z. Wang, M. Choi, K. Lee, K. Park, Z. Liu, A. Biswas, J. Han, S. Du, and E. Alon, “An Output Bandwidth Optimized 200 Gb/s PAM-4 100 Gb/s NRZ Transmitter with 5-Tap FFE in 28nm CMOS,” IEEE J. Solid-State Circuits, Special Issue on the 2021 International Solid State Circuits Conference (ISSCC 2021), Vol. 57, No. 1, pp. 21-31, Sep. 2021.

J. Han, W. Bae, E. Y. Chang, Z. Wang, B. Nikolić, and E. Alon, “LAYGO: A Template-and-Grid-Based Layout Generation Engine for Advanced CMOS Technologies,” IEEE Trans. Circuits Syst. I: Regular Papers, vol. 68, no. 3, pp. 1012–1022, Mar. 2021.

Prior to 2021

[JSSC’19, ASSCC’19] S. Bailey, P. Rigge, J. Han, R. Lin, E. Chang, H. Mao, Z. Wang, C. Markley, A. Izraelevitz, A. Wang, N. Narevsky, W. Bae, S. Shauck, S. Montano, J. Norsworthy, M. Razzaque, W. H. Ma, A. Lentiro, M. Doerflein, D. Heckendorn, J. McGrath, F. DeSeta, R. Shoham, M. Stellfox, M. Snowden, J. Cole, D. Fuhrman, B. Richards, J. Bachrach, E. Alon, and Borivoje Nikolić, “A Mixed-Signal RISC-V Signal Analysis SoC Generator with a 16nm FinFET Instance,” IEEE J. Solid-State Circuits, Special Issue on the 2018 IEEE Asian Solid-State Circuits Conference (ASSCC 2018), vol. 54, no. 10, pp. 2786-2801, Jul. 2019.
[JSSC’19, ESSCIRC’18] A. Wang, W. Bae, J. Han, S. Bailey, P. Rigge, O. Ocal, Z. Wang, K. Ramchandran, E. Alon, and B. Nikolić, “A Real-Time, 1.89-GHz Bandwidth, 175-kHz Resolution Sparse Spectral Analysis RISC-V SoC in 16-nm FinFET,” IEEE J. Solid-State Circuits, Special Issue on the 2018 IEEE European Solid-State Circuits Conference (ESSCIRC 2018), vol. 54, no. 7, pp. 1993-2008, Jun. 2019.
[SSCL’18, VLSI’18] E. Chang, N. Narevsky, J. Han, and E. Alon, “An Automated SerDes Frontend Generator Verified with a 16nm Instance Achieving 15 Gb/s at 1.96 pJ/bit,” IEEE Solid-State Circuits Lett., Special Issue on the 2018 Symposium on VLSI Circuits (VLSIC 2018) , vol. 1, no. 12, pp. 245-248, Dec. 2018.
[TIE’18] W. Bae, H. Ju, K. Park, J. Han, and D.-K. Jeong, “A Supply-Scalable Serializing Transmitter with Controllable Output Swing and Equalization for Next Generation Standards,” IEEE Trans. Ind. Electron., vol. 65, no. 7, pp. 5979-5989, Jul. 2018.
[JSSC’17, ISSCC’17] J. Han, Y. Lu, N. Sutardja, and E. Alon, “Design Techniques for a 60-Gb/s 288-mW NRZ Transceiver With Adaptive Equalization and Baud-Rate Clock and Data Recovery in 65-nm CMOS Technology,” IEEE J. Solid-State Circuits, Special Issue on the 2017 International Solid State Circuits Conference (ISSCC 2017), vol. 52, no. 12, pp. 3474-3485, Dec. 2017.
[JSSC’17, ISSCC’17] J. Im, D. Freitas, A. Roldan, R. Casey, S. Chen, A. Chou, T. Cronin, K. Geary, S. McLeod, L. Zhou, I. Zhuang, J. Han, S. Lin, P. Upadhyaya, G. Zhang, Y. Frans, and K. Chang, “A 40-to-56 Gb/s PAM-4 Receiver with Ten-Tap Direct Decision-Feedback Equalization in 16-nm FinFET,” IEEE J. Solid-State Circuits, Special Issue on the 2017 International Solid State Circuits Conference (ISSCC 2017), vol. 52, no. 12, pp. 3486-3502, Dec. 2017.
[JSSC’16, VLSI’15] J. Han, Y. Lu, N. Sutardja, K. Jung, and E. Alon, “Design Techniques for a 60 Gb/s 173 mW Wireline Receiver Frontend in 65 nm CMOS Technology,” IEEE J. Solid-State Circuits, Special Issue on the 2015 Symposium on VLSI Circuits (VLSIC 2015), vol. 51, no. 4, pp. 871-880, Apr. 2016.
[TCPMT’13] W. Y. Shin, G. M. Hong, H. Lee, J. D. Han, K. S. Park, D. H. Lim, S. Kim, D. Shim, J. H. Chun, D. K. Jeong, and S. Kim, “4-Slot, 8-Drop Impedance-Matched Bidirectional Multidrop DQ Bus With a 4.8-Gb/s Memory Controller Transceiver,” IEEE Trans. Compon., Packag. and Manuf. Technol., vol. 3, no. 5, pp. 858-869, May. 2013.

Peer-reviewed Conference Papers

2025

(accepted) Y. Jo, H. Kim, Y. Choi, J. Park, M. Kwak, and J. Han, “A 32-50Gb/s/pin Single-Ended PAM-4 Transmitter with ZQ-Based FFE and PAM-4 LSB DBI-DC Encoding,” in IEEE Int. Solid-State Circuits Conf. (ISSCC 2025), Feb. 2025.

(accepted) Y. Jo, T. Kang, J. Yang, and J. Han, “A 500-MS/s 8-bit SAR ADC Generated from an Automated Layout Generation Framework in 14-nm FinFET Technology,” in Proceedings of Asia South Pacific Des. Autom. Conf. (ASPDAC 2025), Jan. 2025.

2024

J. Park, M. Kim, and J. Han, “pyngspice: A High-performance Python Binding for Ngspice”, in Workshop on Open-Source EDA Technology (WOSET), Nov. 2024.

S. Lee, H. Seo, S. Son, S. Yeom, and J. Han, “A 102-Gb/s/lane 1.4-Vppd Linear Range PAM-8 Receiver Frontend With Multi-Path Continuous-Time Linear Equalization in 28-nm CMOS,” in IEEE Int. Symp. Integr. Circuits Syst. (ISICAS 2024), Oct. 2024.

H. Kim, Y. Jo, S. Lee, E. Lee, Y. Choi, J. Park, M. Kwak, J. Choi, Y. Choi, and J. Han, “A 32-Gb/s Single-Ended PAM-4 Transceiver With Asymmetric Termination and Equalization Techniques for Next-Generation Memory Interfaces,” in IEEE Int. Symp. Integr. Circuits Syst. (ISICAS 2024), Oct. 2024.

G. You, Y. Byun, S. Lim, and J Han, “Interactive and Automatic Generation of Primitive Custom Circuit Layout Using LLMs”, in 6th ACM/IEEE International Symposium on Machine Learning for CAD (MLCAD), Work-In-Progress Presentation, Sep. 2024.

J. Nam, J. Han, and H. Kim, “Low-Power Encoding for PAM-3 DRAM Bus,” in Int. Conf. Synth., Model., Anal. Simul. Methods, Appl. Circuit Des. (SMACD 204), Jul. 2024.

Z. Wang, M. Choi, P. Kwon, K. Lee, B. Yin, Z. Liu, K. Park, A. Biswas, J. Han, S. Du, E. Alon, “A 24.6-29.6GHz Hybrid Sub-Sampling PLL with Tri-State Integral Path Achieving 44fs Jitter and -254.8dB FOM in 28nm CMOS,” in IEEE Int. Symp. Circuits and Syst. (ISCAS 2024), May. 2024.

2023

J. Yang, E. Song, S. Hong, D. Lee, S. Lee, H. Im, T. Shin, and J. Han, “A 100Gb/s 1.6Vppd PAM-8 Transmitter with High-Swing 3+1 Hybrid FFE Taps in 40nm,” in IEEE Int. Solid-State Circuits Conf. (ISSCC 2023), Feb. 2023.

2022

Y. Su, S. Lee, E. Song, D. Kim, J. Han, and H. Kim, “Energy-Efficient Bus Encoding Techniques for Next-Generation PAM-4 DRAM Interfaces,” in Proceedings of the 40th IEEE Int. Conf. Comput. Des. (ICCD 2022), Oct. 2022.

E. Song, J. Yang, S. Hong, and J. Han, “A 32-Gb/S High-Swing PAM-4 Current-Mode Driver with Current-Bleeding Cascode Technique and Capacitive-Coupled Pre-Drivers in 40-nm CMOS for Short-Reach Wireline Communication,” in IEEE Int. Midwest Symp. on Circuits and Syst., Aug. 2022.

Z. Wang, M. Choi, P. Kwon, K. Lee, B. Yin, Z. Liu, K. Park, A. Biswas, J. Han, S. Du, E. Alon, “A 200Gb/s PAM-4 Transmitter with Hybrid Sub-Sampling PLL in 28nm CMOS Technology,” in IEEE Int. Symp. VLSI Circuits, Jun. 2022.

Z. Wang, M. Choi, J. Wright, K. Lee, Z. Liu, B. Yin, J. Han, S. Du, E. Alon, “A Ring-Oscillator Sub-Sampling PLL with Hybrid Loop Using Generator-Based Design Flow,” in IEEE Int. Symp. Circuits and Syst., May. 2022.

2021

Taeho Shin and Jaeduk Han, “A SCAN Chain Generator for Verification of Full-Custom Integrated Circuits,” in IEEE 18th Int. SoC Design Conf., Oct. 2021.

Dongjun Lee and Jaeduk Han, “Design Techniques for Area-efficient Two-Stacked Current Sources in Nanometer CMOS Technology,” in IEEE 18th Int. SoC Design Conf., Oct. 2021.

Gaeryun Sung and Jaeduk Han, “High-speed StrongARM-latch-based Bang-bang Phase Detector in 40-nm CMOS Technology,” in IEEE 18th Int. SoC Design Conf., Oct. 2021.

M. Choi, Z. Wang, K. Lee, K. Park, Z. Liu, A. Biswas, J. Han, and E. Alon, “An output bandwidth optimized 200Gb/s PAM-4 / 100Gb/s NRZ transmitter with 5-Tap FFE in 28nm CMOS,” in IEEE Int. Solid-State Circuits Conf., Feb. 2021.

Y. Yoon, D. Han, S. Chu, S. Lee, J. Han and J. Chun, “Process-Portable and Programmable Layout Generation of Digital Circuits in Advanced DRAM Technologies,” in Proc. Design, Autom. Test Eur. Conf., Feb. 2021.

2020

Taeung No and Jaeduk Han, “Design Techniques for Robust and Area-efficient Current Sources in Nanometer CMOS Technology,” in IEEE 17th Int. SoC Design Conf., Oct. 2020.

Prior to 2020

[ISOCC’19, Invited] Jaeduk Han, Eric Chang, Elad Alon, “Design and Automatic Generation of High-Speed Circuits for Wireline Communications,” in IEEE 16th Int. SoC Design Conf., 8 Oct. 2019, pp. 40-41.
[ESSCIRC’19] Nicholas Sutardja, Jaeduk Han, Nathan Narevsky, Elad Alon, Borivoje Nikolić, “A 2-tap switched capacitor FFE transmitter achieving 1-20 Gb/s at 0.72-0.62 pJ/bit,” in IEEE Eur. Solid-State Circuits Conf., Sep. 2019, pp. 273-276.
[CICC’19] Jaeduk Han, Eric Chang, Stevo Bailey, Zhongkai Wang, Woorham Bae, Angie Wang, Nathan Narevsky, Amy Whitcombe, Pengpeng Lu, Borivoje Nikolic, Elad Alon, “A Generated 7GS/s 8b Time-Interleaved SAR ADC with 38.2dB SNDR at Nyquist in 16nm CMOS FinFET,” in IEEE Custom Integr. Circuits Conf., 17 Apr. 2019, pp. 1-4.
[ASSCC’18] Stevo Bailey, Jaeduk Han, Paul Rigge, Richard Lin, Eric Chang, Howard Mao, Zhongkai Wang, Chick Markley, Adam Izraelevitz, Angie Wang, Nathan Narevsky, Woorham Bae, Steve Shauck, Sergio Montano, Justin Norsworthy, Munir Razzaque, Wen Hau Ma, Akalu Lentiro, Matthew Doerflein, Darin Heckendorn, Jim McGrath, Franco DeSeta, Ronen Shoham, Mike Stellfox, Mark Snowden, Joseph Cole, Dan Fuhrman, Brian Richards, Jonathan Bachrach, Elad Alon, and Borivoje Nikolic ́, “A Generated Multirate Signal Analysis RISC-V SoC in 16nm FinFET,” in IEEE Asian Solid-State Circuits Conf,, Nov. 2018, pp. 285-288.
[ECCE’18] Yongjun Li, Jaeduk Han, Seth. A. Sanders, “A Low-Cost AC Direct LED Driver with Reduced Flicker using Triac,” in IEEE Energy Convers. Congress and Exposition, Sep. 2018, pp. 4738-4743.
[ESSCIRC’18] Angie Wang, Woorham Bae, Jaeduk Han, Stevo Bailey, Paul Rigge, Orhan Ocal, Zhongkai Wang, Kannan Ramchandran, Elad Alon, Borivoje Nikolić, “A Real-Time, Analog/Digital Co-Designed 1.89-GHz Bandwidth, 175-KHz Resolution Sparse Spectral Analysis RISC-V SoC in 16-nm FinFET,” in IEEE European Solid-State Circuits Conference, Sep. 2018.
[VLSI’18] Eric Chang, Nathan Narevsky, Jaeduk Han, Elad Alon, “An Automated SerDes Frontend Generator Verified with a 16nm Instance Achieving 15 Gb/s at 1.96 pJ/bit,” in IEEE Int. Symp. VLSI Circuits, Jun. 2018, pp. 153-154.
[CICC’18, Invited] Eric Chang, Jaeduk Han, Woorham Bae, Zhongkai Wang, Nathan Narevsky, Guanghua Shu, Frankie Liu, Borivoje Nikolić, Elad Alon, “BAG2: A Process-Portable Framework for Generator-Based AMS Circuit Design,” in IEEE Custom Integr. Circuits Conf., Apr. 2018, pp.1-8.
[ASSCC’17] Angie Wang, Brian Richards, Palmer Dabbelt, Howard Mao, Stevo Bailey, Jaeduk Han, Eric Chang, James Dunn, Elad Alon, Borivoje Nikolić, “A 0.37mm2 LTE/Wi-Fi Compatible, Memory-Based, Runtime-Reconfigurable 2n3m5k FFT Accelerator for RISC-V Rocket Core in 16nm FinFET,” in IEEE Asian Solid-State Circuits Conf., Nov. 2017, pp. 305-307.
[ISSCC’17] Jaeduk Han, Yue Lu, Nicholas Sutardja, Elad Alon, “A 60Gb/s 288mW NRZ Transceiver with Adaptive Equalization and Baud-Rate Clock and Data Recovery in 65nm CMOS Technology,” in IEEE Int. Solid-State Circuits Conf., Feb. 2017, pp. 112-113.
[ISSCC’17] J. Im, D. Freitas, A. Roldan, R. Casey, S. Chen, A. Chou, T. Cronin, K. Geary, S. McLeod, L. Zhou, I. Zhuang, J. Han, S. Lin, P. Upadhyaya, G. Zhang, Y. Frans, K. Chang, “A 40-to-56Gb/s PAM-4 Receiver with 10-Tap Direct Decision-Feedback Equalization in 16nm FinFET,” in IEEE Int. Solid-State Circuits Conf., Feb. 2017, pp. 114-115.
[VLSI’15] Jaeduk Han, Yue Lu, Nicholas Sutardja, Kwangmo Jung, Elad Alon, “A 60Gb/s 173mW Receiver Frontend in 65nm CMOS technology,” in IEEE Int. Symp. VLSI Circuits, Jun. 2015, pp. 230-231.
[ISSCC’11] Woo-Yeol Shin, Gi-Moon Hong, Hyongmin Lee, Jae-Duk Han, Sunkwon Kim, Kyu-Sang Park, Dong-Hyuk Lim, Jung-Hoon Chun, Deog-Kyoon Jeong, Suhwan Kim, “A 4.8Gb/s impedance-matched bidirectional multi-drop transceiver for high-capacity memory interface,” in IEEE Int. Solid-State Circuits Conf., Feb. 2011, pp.494-496.
[ASSCC’10] J. D. Han, W-Y. Shin, W-S. Choi, J-H. Chun, S. Kim, D-K. Jeong, “A 5-Gb/s digitally controlled 3-tap DFE receiver for serial communications,” in IEEE Asian Solid-State Circuits Conf., Nov. 2010, pp.1-4.

Patents

J. Han, S. Lee, “High-speed amplifier”, filed, KR10-2023-0005221.
J. Han, H. Im, T. Sim, S. Yeom, “High-speed sampler and its data transmission method”, filed, KR10-2022-0151586.
J. Han, S. Park, E. Song, J. Yang, Y. Oh, “Method and appartus of data transmission system with reduced supply noise”, filed, KR10-2022-0100356.
J. Han, E. Song, S. Park, “Transition limited pulse amplitude modulation signaling,” filed, KR10-2022-0048694.
J. Han, W. Shin, H. Seo, “Feed-forward equalizer transmitter,” filed, KR10-2022-0040923.
J. Han, D.Lee, T.Shin, D.Kim, G. Sung, “Apparatus of generating semiconductor integrated circuits,” filed, KR10-2022-0074725.
[삼성전자 전략특허상] J. Han, S.Lee, H. Kim, J. Yang, “A semiconductor apratus”, filed / USXXXXXXXX.
J. Han, S.Lee. E. Song, K. Park, “Passive continuous time linear equalizer,” filed, KR10-2021-0165307.
J. Han, J. Yang. H. Kim. H. Seo, “High-speed 4:1 multiplexer,” KR10-2420430.
J. Han, E. Song. T. Shin. S. Hong, “Feed-forward equalizer using shunt mosfets”, filed, KR10-2021-0174816.
[SK하이닉스 우수특허상] J. Han, E. Song. G. Park. J. Kim, “Continuous time linear equalizer”, filed, KR10-2021-0170049 / USXXXXXXXX.
Y. Yoon, J. Han, “Method of generating layout for integrated circuits,” filed, KR10-2021-0086673 / USXXXXXXXX.
J. Han, E. Song, S. Lee, Y. Cho, H. Seo, H. Kim, “Data inversion circuit for DBI-AC encoded PAM4 signaling,” filed, KR10-2021-0112910 / US17896471.
J. Han, E. Song, S. Lee, Y. Cho, H. Seo, H. Kim, “Data inversion circuit for DBI-DC encoded PAM4 signaling,” filed, KR10-2021-0112909 / US17896549.
J. Han, G. Sung, “High-speed clock and data recovery circuit,” filed, KR10-2021-0042984.
J. Han, G. Park, E. Song, “Method of stabilizing internal voltages of cascode current-mode logic circuits,” filed, KR10-2021-0042985.
Y. Song, J. Han, S. Kim, “GGNMOS-based sensing scheme,” filed, KR10-2021-0009876.
Y. Song, J. Han, S. Kim, “Feedforward-path-based sensing scheme,” filed, KR10-2021-0009875.
J. Han, E. Song, “High-order PAM drive circuit,” KR102292736 / PCT-KR2021-017559.
J. Han, J. Yang, “High speed multiplexer,” KR102295709 / PCT-KR2021-017563.
J. Han, T. No, “Current mirror,” filed, KR10-2020-0173740.
J. Han, “Current mode logic circuit,” KR102295708.
J. Han, “Current mode logic circuit,” KR1023657292 / PCT-KR2020-017832 / US17802555.
F.Farbiz, J.Han, P.Singh, “High Speed ESD Protection Circuit”, US11322935.
J. Han, W. Liu, W. Liu, M.-S. Chen, S. K. Maheshwari, V. Varma, S. Bhosekar, L. Zhong, “Serial data receiver with sampling clock skew compensation,” US10972107.
J. Han, J. Im, “Low-Power Decision Threshold Control for High-Speed Signaling,” US10193540.
J. Seo, H. Kim, H. Ju, H. Kim, J. D. Han, D. K. Jeong, “LED Lighting System and AC-DC Converting Circuit used thereto,” KR101340297.
J. D. Han, H. C. Kim, D. K. Jeong, “Voltage supporting type LED lighting system,” KR101371247.
J. D. Han, B. T. Jang, “LED Lighting System for decreasing the variation in current to that in temperature,” KR101340295.
J. D. Han, K. R. Ahn, “Voltage detection LED lighting system,” KR101348966.
J. D. Han, K. R. Ahn, “LED lighting system having common current source,” KR101326479.
J. D. Han, K. R. Ahn, “LED lighting system for improving lighting amount and operating characteristics,” KR101321343.
J. D. Han, K. R. Ahn, “LED lighting system for improving lighting amount and reducing layout area,” KR101307789.
J. D. Han, “LED illuminating apparatus having enhanced quantity of light,” US9101016, PCT/KR2013/000523.
J. D. Han, “LED lighting system for improving voltage current non-harmony,” KR101359890.
J. D. Han, J. W. Lee, “Current detection LED lighting system,” KR101285644.
B. T. Jang, J. D. Han, “LED lighting system for improving modulation index,” KR101189102.

back